| BODY LENGTH | 0.265 INCHES MAXIMUM |
| DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, J-K, OR INPUT |
| FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INCLOSURE MATERIAL | CERAMIC |
| INPUT CIRCUIT PATTERN | 9 INPUT |
| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| MAXIMUM POWER DISSIPATION RATING | 40.0 MILLIWATTS |
| OPERATING TEMP RANGE | +0.0 TO 75.0 CELSIUS |
| STORAGE TEMP RANGE | -65.0 TO 200.0 CELSIUS |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TERMINAL TYPE AND QUANTITY | 14 FLAT LEADS |
| TEST DATA DOCUMENT | 05869-717320-18 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| TIME RATING PER CHACTERISTIC | 40.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 20.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 5.5 VOLTS MAXIMUM POWER SOURCE |
| BODY HEIGHT | 0.030 INCHES MINIMUM AND 0.080 INCHES MAXIMUM |
| BODY WIDTH | 0.265 INCHES MAXIMUM |