| BODY HEIGHT | 0.030 INCHES MINIMUM AND 0.070 INCHES MAXIMUM |
| BODY LENGTH | 0.240 INCHES MINIMUM AND 0.260 INCHES MAXIMUM |
| BODY WIDTH | 0.120 INCHES MINIMUM AND 0.150 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-84 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 6 GATE, NAND |
| FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND LOW POWER AND MEDIUM SPEED |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | HEX 1 INPUT |
| OUTPUT LOGIC FORM | DIODE-TRANSISTOR LOGIC |
| MAXIMUM POWER DISSIPATION RATING | 132.0 MILLIWATTS |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| PRECIOUS MATERIAL | GOLD |
| PRECIOUS MATERIAL AND LOCATION | TERMINALS GOLD |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TERMINAL SURFACE TREATMENT | GOLD |
| TIME RATING PER CHACTERISTIC | 48.00 NANOSECONDS NOMINAL PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 48.00 NANOSECONDS NOMINAL PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |