| BODY HEIGHT | 0.140 INCHES MINIMUM AND 0.180 INCHES MAXIMUM |
| BODY LENGTH | 0.660 INCHES MINIMUM AND 0.785 INCHES MAXIMUM |
| BODY WIDTH | 0.220 INCHES MINIMUM AND 0.280 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | T0-116 JOINT ELECTRON DEVICE ENGINEERING COUNCIL |
| DESIGN FUNCTION AND QUANTITY | 1 FLIP-FLOP, J-K/R-S, CLOCKED, MASTER SLAVE |
| FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND POSITIVE OUTPUTS AND ASYNCHRONOUS AND SYNCHRONOUS AND W/BUFFERED OUTPUT AND EDGE TRIGGERED AND W/CLEAR AND RESETTABLE |
| INCLOSURE CONFIGURATION | DUAL-IN-LINE |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | 7 INPUT |
| OUTPUT LOGIC FORM | DIODE-TRANSISTOR LOGIC |
| MAXIMUM POWER DISSIPATION RATING | 70.0 MILLIWATTS |
| OPERATING TEMP RANGE | -55.0 TO 125.0 CELSIUS |
| STORAGE TEMP RANGE | -65.0 TO 150.0 CELSIUS |
| TERMINAL TYPE AND QUANTITY | 14 PRINTED CIRCUIT |
| TERMINAL SURFACE TREATMENT | SOLDER |
| TEST DATA DOCUMENT | 92059-900305 DRAWING (THIS IS THE BASIC GOVERNING DRAWING, SUCH AS A CONTRACTOR DRAWING, ORIGINAL EQUIPMENT MANUFACTURER DRAWING, ETC.; EXCLUDES ANY SPECIFICATION, STANDARD OR OTHER DOCUMENT THAT MAY BE REFERENCED IN A BASIC GOVERNING DRAWING) |
| TIME RATING PER CHACTERISTIC | 75.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 75.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |